Theory of Operation 4-1 ********************************************************************* * * * T V S 7 0 1 B T H E O R Y O F O P E R A T I O N * * * ********************************************************************* T H E O R Y O F O P E R A T I O N The TVS701 uses a MC68705R3 microcomputer. Most of the functionality of the system is provided by firmware within the Microcomputer Unit (MCU). This section will describe the external circuitry of the TVS701. The system clock is provided by a 3.579545 Mhz crys- tal oscillator composed of one CMOS inverter gate (4069) (IC4) and associated components. The output of the clock goes through two buffer stages (another stage of IC4) to the clock input of the MCU. The clock also drives a divider chain consisting of two 74HC4040 type 12 stage ripple counters U5 and U6. Output Q3 of U5 provides a 447.4 Khz clock which is used for the DTMF decoder. Output Q12 pro- vides a slow clock which drives U6. U6 is used for the "watchdog" function. This func- tion provides a reliable means of starting and restarting the MCU regardless of previous power supply fluctuations. If the microprocessor suffers a transient failure and stops running the software, the watchdog will likewise restart it. This method is superior to the traditional method of simply connecting a capacitor to the processor reset to generate a pulse on power-up. U6 counts up until output Q12 goes posi- tive. At this point the processor RESET (RST*) signal is asserted, and the processor is stopped and reset. When Q12 goes back to negative, the processor then starts. In normal operation, the processor changes the state of its output on pin 36 every 100 msec. This drives a transistor driver (Q1) which pulses capacitor C1, and incidentally drives the green "heartbeat" LED (LE1). When C1 pulses high, U6 is reset, and thus fails to reach a count high enough to turn its Q12 out- put positive. Thus, in the watchdog circuit, either the pro- cessor resets the watchdog (normal operation), or the watch- dog resets the processor (restart). Theory of Operation 4-2 DTMF decoding is provided by a single chip decoder of type M956 (U3). The M956 requires around 100mv (non- critical) of audio on its input pin 12. It is supplied an accurate 447.4 Khz clock on pin 17. When a valid digit is recognized, pin 18 of U3 goes positive, resulting (after an inverter) in a low level on pin 3 of the MCU. Pin 18 stays high until the tone goes away. During the time Pin 18 is high, a Binary code representing the digit is present on outputs D0 through D3 (Pins 1, 22, 21, 10 of U5). This code is used by the processor for control functions. Parameters are stored in a non-volatile memory, the NMC9306 EEPROM, U7. This chip guarantees that parameters and controller states such as ID's, timer values, enable/disable states, etc. are not lost over power off. This chip is interfaced with serial data on its DI and DO pins, a software generated clock on SK, and a chip select on CS. The chip will tolerate about 10000 erase/write cycles before failing, which is enough for normal repeater operation. The chip is only written when a control function changes some parameter or state. For controllers which will be changed very frequently, a mode is provided which will not automati- cally write the changes to the EEPROM, but rather will write certain state changes only when explicitely commanded. Analog inputs are connected via scaling potentiome- ters (A0 - A3) to the Analog-to-Digital inputs of the MPU (pins 21-24). The A/D measures the ratio of the input vol- tage to the voltage on pin 19 of the processor. Pin 19 is supplied with 5.00 Volts by a precision voltage reference (U8). Conversion scale is selected with software, and then calibrated using the scaling potentiometers. Care should be taken to avoid exceeding 5.0 Volts on the processor analog input pins 21-24. Digital inputs are connected directly to processor pins 9-11 and 17-18. These inputs are pulled up by 10K resistors. The voltage levels on these inputs must meet TTL specifications, and may not exceed 5.0 Volts. Digital outputs are stored in latch U2 (74HC374) and are asserted by open collector 2N2222 transistors Q2 - Q8. When the processor needs to change an output bit, it sets suitable values on processor pins 33 - 40, and then toggles pin 27 (LCLK) to clock the data into the latch (U2). Theory of Operation 4-3 I N C A S E O F D I F F I C U L T Y (1) If the "HEART" LED (LE1) is pulsing several times per a second, the processor is probably OK. Verify the levels into the DTMF decoder, and make sure your DTMF gen- erator works with some other, known working, system. You can tell if the DTMF decoder chip (U3) is decoding your tones by observing LED LE4. If it changes lights when you enter tones, it is working. If it doesn't work, check the clock on pin 17 of U3. It should be 447.4 Khz 0 to 5Volts. If it is not accurate (1%), the DTMF decoder will not work. (2) If the "HEART" LED is not pulsing, something is badly wrong! First you should determine if the correct power is getting to all IC's. Then, see if the 3.579545 oscillator is running (IC4 Pin 12), and make sure it is reaching the processor (Pin 5). Make sure that the watchdog is working. It should apply a +5 volt reset signal to pin 2 of the processor every .1 seconds, and then remove that sig- nal. If this does not happen, the processor may never start. Once the processor starts, it must reset the watchdog before the next reset signal occurs. The circuit between pin 36 of the processor and pin 11 of U6 is used for that pur- pose. If pin 36 of the processor is toggling, the processor is working. The green LED should pulse with pin 36. (3) If all else fails, look at the schematic, and check the voltages and waveforms throughout the circuit. Theory of Operation 4-4